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| Micrel, Inc. 3.3V AnyRate(R) MUX/DEMUX Up to 2.7GHz SY87724L SY87724L FEATURES s Protocol transparent MUX/DEMUX operation up to 2.7GHz s Programmable to 4, 5, 8, or 10 bit parallel interfaces s Differential clock and serial inputs/outputs s Easily controlled by framer logic s Synchronous frame boundary indication s HSPC (High Speed PECL Compatible) inputs and outputs s 3.3V power supply s Available in 80-pin LQFP-PQ2 package DESCRIPTION The SY87724L is a complete serial data multiplexer and demultiplexer, capable of operating at up to 2.7GHz. The device provides for muxing and demuxing to 4, 5, 8, or 10 bit wide buses. The SY87724L can accept a synchronous code group or octet boundary input, and uses this input for parallel data alignment. The SY87724L is manufactured in Micrel's high performance ASSET2TM silicon bipolar process. Micrel provides a complete protocol transparent solution with the AnyRate(R) SY87721L CDR/CMU SY87729L, and the SY87724L integrated MUX/DEMUX. APPLICATIONS s s s s s s OC-3, OC-12, OC-48, ATM, InfiniBand Gigabit Ethernet Fibre Channel, 2X Fibre Channel SMPTE-259 and 292 Proprietary optical transport ITU G. 975 Solutions SYSTEM BLOCK DIAGRAM SY889x3 FIBER PIN DIODE TIA POST AMP SY87721L RDATA SY87724L 4, 5, 8, 10 bits RCLK DEMUX LOCK AnyRateTM CDR TCLK One REF_XTAL MUX 4, 5, 8, 10 bits SY87729L REF_CLK CMU AnyClockTM Fractional Synthesizer SEL CD SY889x2 FIBER LASER DIODE LASER DIODE DRIVER AnyRate is a registered trademark of Micrel, Inc. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 Rev.: D Amendment: /0 1 Issue Date: March 2006 Micrel, Inc. SY87724L PACKAGE/ORDERING INFORMATION Ordering Information(1) Part Number SY87724LHI SY87724LHY(2) Package Type H80-1 H80-1 Operating Range Industrial Industrial Package Marking SY87724LHI SY87724LHY with Pb-Free bar line indicator Lead Finish Sn-Pb Matte Tin Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Pb-Free package is recommended for new designs. DPOUTCK+ MPF4+ MPF4- VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 GND VCC NC NC NC SIZ0 SIZ1 SIZ2 MP0 MP1 MP2 MP3 MP4 MP5 MP6 MP7 MP8 MP9 VCC VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND DPOUTCK- DP0+ DP0- 60 59 58 57 56 55 54 53 52 MTXCLK+ MTXCLK- MPF0+ MPF0- MPF1+ MPF1- MPF2+ MPF2- MPF3+ MPF3- GND VCCO VCC DP1+ DP1- DP2+ DP2- VCCO VCCO DP3+ DP3- DP4+ DP4- DP5 DP6 DP7 DP8 DP9 VCCO DCKIN- DCKIN+ VCCO 80-PIN LQFP-PQ2 51 50 49 48 47 46 45 44 43 42 41 NC NC MPINCK+ VCC GND MSOUT+ MSOUT- GND LPBK VCCO DFMIN+ DFMIN- MPINCK- DSIN+ 80-Pin EPAD TQFP (H80-1) M9999-031506 hbwhelp@micrel.com or (408) 955-1690 2 DSIN- VCC VCC GND NC NC Micrel, Inc. SY87724L FUNCTIONAL BLOCK DIAGRAM DEMUX DSIN Mux MSOUT (From Mux) Serial In Parallel Out Shift Register (5 bits) 5 Parallel In Parallel Out Register (5 bits) DCKIN Mux MTKCLK (From Mux) DFMIN Primary Divider (/4 or /5) Mux MSYNOUT (From Mux) SIZ0 SIZ1 SIZ2 Demux Strobe Generator LPBK Demux Internal Control 5 Parallel In Parallel Out Register (5 bits) 5 Parallel In Parallel Out Register (5 bits) 5 DP0-4 Parallel In Parallel Out Register (5 bits) 5 Parallel In Parallel Out Register (5 bits) 5 DP5-9 Delay DPOUTCK M9999-031506 hbwhelp@micrel.com or (408) 955-1690 3 Micrel, Inc. SY87724L FUNCTIONAL BLOCK DIAGRAM MUX MTXCLK MP0-4 5 Parallel In Parallel Out MPF0-4 5 Parallel In Parallel Out Register (5 bits) MP0-4 5 Parallel In Parallel Out Register (5 bits) Serial and Parallel In Serial Out Shift Register (5 bits) Mux 5 MSOUT MP5-9 5 Parallel In Parallel Out Register (5 bits) SIZ0 MPINCK SIZ1 SIZ2 Mux Strobe Generator Load/Shift MSYNOUT (to Demux) M9999-031506 hbwhelp@micrel.com or (408) 955-1690 4 Micrel, Inc. SY87724L PIN NAMES COMMON LPBK - TTL Input This pin defines whether a device exhibits local loopback or not, as per the following table. Loopback internally connects mux serial out to demux serial in, thus the user may expect mux side parallel data to appear on the demux parallel output pins. LPBK 0 1 Functioning Loopback Normal DP0 through DP4 - Differential PECL Output These signals may be used as either differential, or singleended. When converting to 4 or 5 bits, speed issues may encourage the use of these signals differentially. When converting to wider than 5 bits, these signals are to be used single-ended. Please refer to the applications section for further details. DP5 through DP9 - PECL Output These are the rest of the parallel output bits, to be used when converting to wider than 5 bits. Which bits are valid depends on the values of SIZ0, SIZ1, and SIZ2. Please refer to the table in the applications section for further details. DPOUTCK - Differential HSPC Output This signal is used to strobe the DP0-9 data. It is used differentially when converting to 4 or 5 bits, and is used single-ended when converting to wider than 5 bits. The clock rate of the line will be determined by the DCKIN signal, and by the setting of the SIZ bits. This output always provides valid differential logic levels. MUX MP0-9 - PECL Input These bits accept data for muxing wider than 5 bits. MPINCK+, used single-ended, determines when this data may change. Please refer to the table in the description for which pins represent what bits for various widths. MPF0-4 - Differential PECL Input These signals are used when muxing 4 or 5 bits of parallel data. MPINCK determines when this data may change. Please refer to the Mux table in the description for which pins represent what bits for various widths. MTXCLK - Differential HSPC Input This is the serial rate clock input to the mux. It determines the rate at which serial data will be shifted out of the mux. MSOUT - Differential PECL Output This signal is the serialized data output. MPINCK - Differential PECL Output This signal indicates when the next set of parallel bits may be presented to the SY87724L for muxing. For muxing wider than 5 bits, MPINCK+ is used single-ended. These signals always provide valid differential clock signals regardless of single-ended or differential data mode. OTHER VCC VCCO GND NC Supply Voltage Output Supply Voltage Ground These pins are reserved and are to be left unconnected. SIZ0, SIZ1, SIZ2 - TTL Input These three signals determine the width of the parallel output, as well as the width of parallel input. The following table describes the parallel width options. Width 4 5 8 10 Undefined SIZ0 0 1 0 1 X SIZ1 0 0 1 1 X SIZ2(1) 0 0 0 0 1 Note: 1. Pin 8 (SIZ2) should always be tied to a TTL logic level LOW. DEMUX DSIN - Differential HSPC Input This is the serial input to the SY87724L demux. It accepts the serial data and converts it to parallel data. It is ignored during loopback. DCKIN - Differential HSPC Input This is the bit rate clock that feeds serial data into the demux shift register. This signal also feeds the demux strobe generator and primary divider, except during loopback. DFMIN - Differential HSPC Input This is the frame alignment input signal. This signal resets the primary divider, as well as the strobe generator. This effectively sets the alignment for the parallel data being demuxed. Usually, DFMIN asserts one DCKIN before a parallel word boundary, and continues to assert one clock before every boundary. However, DFMIN need only occur once for proper operation. Should DFMIN assert at other than a previously set boundary, the DPOUTCK signal will always occur later than would be expected. That is, there will never be a short DPOUTCK pulse. Note: 1. All differential outputs always provide valid differential logic levels regardless of differential or single-ended use. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 5 Micrel, Inc. SY87724L DESCRIPTION General The SY87724L MDM is designed to perform muxing and demuxing at up to 2.7GHz speeds. The device can simultaneously mux and demux up to 10 bits of full duplex data. In addition, a full parallel-to-parallel loopback function is implemented, such that parallel data out will loop back to parallel data in, with the device internally connecting the serial output to the serial input. Narrow Demux In this example, serial data is converted into 4 or 5 bit wide data. Because this can result in very high data rates on the parallel outputs, they are differential. The DFMIN input indicates, synchronously with DCKIN, and one clock ahead, the start of a 4 or 5 bit boundary. DP0-4 DSIN DCKIN DFMIN DPOUTCK MDM DP0-4+ DSIN DCKIN DFMIN DPOUTCK+ MDM DP5-9 Figure 2. Wide Demux As in the narrow case, DPOUTCK will never assert twice in 8 or 10 DCKIN cycles. Should a DFMIN assertion change the MDM's 8 or 10 bit boundary, DPOUTCK assertion will be delayed and there will never be a short assertion. For 8 bit output, DP4 and DP9 are not used. The following table summarizes the available bit widths. The right column shows the parallel bits, in sequence from first in serially, to last in. Width 4 5 8 10 Sequence DP0, DP1, DP2, DP3 DP0, DP1, DP2, DP3, DP4 DP0+, DP1+, DP2+, DP3+, DP5, DP6, DP7, DP8 DP0+, DP1+, DP2+, DP3+, DP4+, DP5, DP6, DP7, DP8, DP9 Figure 1. Narrow Demux Every DFMIN assertion will trigger a new 4 or 5 bit boundary. Should only one DFMIN assertion occur, then DPOUTCK will continue to assert every 4 or 5 DCKIN clocks. Should a subsequent DFMIN assertion reset the 4 or 5 bit boundary, then DPOUTCK will always result in a longer assertion, not a shorter one. For example, if a subsequent DFMIN resets a 5 bit boundary after the second bit in relation to a previous boundary, then the next DPOUTCK will always occur 7 DCKIN later, never 2 DCKIN later. For four bit output, DP5 are not used. Wide Demux The more typical case will be to convert the serial data stream into 8 or 10 bit wide data. Because the worst case parallel transfer rate is on the order of 250 to 340 Megatransfers per second, single ended parallel output is preferred. Thus, only the single-ended side of the differential outputs is used. This example is much like the narrow demux, except now DFMIN indicates 8 or 10 bit boundaries. Narrow Mux In this scenario, 4 or 5 bit wide parallel data is converted to a serial bit stream. Because this can result in very high data rates on the parallel inputs, they are differential. In this mode of operation, there is no external synchronization, and the MPINCK signal pair has arbitrary phase with respect to the MTXCLK clock, which clocks the mux output shift register. MTXCLK MSOUT MPF0-4 MDM MPINCK Figure 4. Narrow Mux MPINCK indicates when MDM is ready to accept more data. It is derived from MTXCLK, with an arbitrary phase relationship. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 6 Micrel, Inc. SY87724L Wide Mux The more typical case will be to convert 8 or 10 bit wide parallel data words into a serial bit stream. Because the worst case parallel input rate is on the order of 250 to 340 Mega-transfers per second, single ended parallel inputs are used. This scenario is much like the narrow mux case, except now MPINCK+ clocks slower, for 8 or 10 bit parallel words. MTXCLK MP0-9 MPINCK+ MDM MSOUT Figure 5. Wide Mux Loopback To ease system design, the SY87724L MDM has the capability to loop parallel data in, through the mux, into the demux, and back to parallel data out. This permits system check-out through to the individual MDM device. Note that, for a full check-out, some form of loopback further down the serial stream is required. Loopback is incorporated into MDM by modifying the serial clock, data, and sync inputs to the demux stage. During loopback, the source of serial information for the demux is changed. The MSOUT, MTXCLK and MSYNOUT are internally muxed to the DSIN, DCKIN, and DFMIN nodes of the demux section. The MSYNOUT signal has the same characteristics as the DFMIN logic expects. This exercises the internal data path, both mux and demux, for MDM, and also the control logic. The parallel data presented to the parallel inputs will appear, some small but unspecified time later, at the parallel outputs. Note that the input data indication is now single ended, and that completely different input pins are used, as compared to the 4 or 5 bit case. The following table summarizes the available bit widths. The right column shows the parallel input bits, such as they will appear in the serial output stream. Width 4 5 8 10 MP* MSOUT DP* DSIN DCKIN DFMIN Sequence MPF0, MPF1, MPF2, MPF3 MPF0, MPF1, MPF2, MPF3, MPF4 MP5, MP6, MP7, MP8, MP0, MP1, MP2, MP3 MP5, MP6, MP7, MP8, MP9, MP0, MP1, MP2, MP3, MP4 * Number of wires depends on the SIZX bits. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 7 Micrel, Inc. SY87724L ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VI IOUT Tstore TA Parameter Power Supply Voltage Input Voltage ECL Output Current Storage Temperature Range Operating Temperature Range --Continuous --Surge Rating -0.5 to +3.8 -0.5 to VCC(2) Unit V V mA C C 50 100 -65 to +150 -40 to +85 NOTES: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The maximum value is specified at VCC up to VCC = +6V. DC ELECTRICAL CHARACTERISTICS(1) VCC = VCCA = 3.15V to 3.45V Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Min. 3.15 -- Typ. 3.3 650 Max. 3.45 750 Unit V mA Condition NOTE: 1. Operating temperature range from -40C to +85C. HSPC DC ELECTRICAL CHARACTERISTICS(1) VCC = VCCA = 3.15V to 3.45V Symbol VIH VIL IIL VOH VOL VOSW Parameter Input HIGH Voltage Input LOWVoltage Input LOW Current Output HIGH Voltage Output LOW Voltage Output Voltage Differential Swing Min. VCC - 1.165 VCC - 1.810 -0.5 VCC - 1.0 VCC - 1.55 0.3 Typ. -- -- -- -- -- -- Max. VCC - 0.880 VCC - 1.475 -- VCC - 0.75 VCC - 1.25 -- Unit V V A V V V VIN = VIL(Min) 50 to VCC -2V 50 to VCC -2V Condition NOTE: 1. Operating temperature range from -40C to +85C. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 8 Micrel, Inc. SY87724L PECL DC ELECTRICAL CHARACTERISTICS(1) VCC = VCCA = 3.15V to 3.45V Symbol VIH VIL IIL VOH VOL VOSW Parameter Input HIGH Voltage Input LOW Voltage Input LOW Current Output HIGH Voltage Output LOW Voltage Output Voltage Differential Swing Min. VCC - 1.165 VCC - 1.810 -0.5 VCC - 1.075 VCC - 1.860 0.6 Typ. -- -- -- -- -- -- Max. VCC - 0.880 VCC - 1.475 -- VCC - 0.830 VCC - 1.570 -- Unit V V A V V V VIN = VIL(Min) 50 to VCC -2V 50 to VCC -2V Condition NOTE: 1. Operating temperature range from -40C to +85C. TTL DC ELECTRICAL CHARACTERISTICS(1) VCC = VCCA = 3.15V to 3.45V Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. 2.0 -- -- -- -- Typ. -- -- -- -- -- Max. -- 0.8 +20 +100 300 Unit V V A A A VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. VIN = 0.5V, VCC = Max. Condition NOTE: 1. Operating temperature range from -40C to +85C. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 9 Micrel, Inc. SY87724L AC ELECTRICAL CHARACTERISTICS VCC = VCCA = 3.15V to 3.45V Symbol fMAX tDCKPWH, tDCKPWH tDSDS tDSDH tDSFS tDSFH tDPDP tDPSP tMCKPWH, tMCKPWL tMPDS tMPDH tMPSS tMPSH tr, tf Parameter Maximum Operating Frequency Demux Clock Pulse Duty Cycle Demux Serial Data Setup Demux Serial Data Hold Demux Serial Frame Setup Demux Serial Frame Hold Demux Parallel Differential Propagation Demux Parallel Single-Ended Propagation Mux Clock Pulse Duty Cycle Mux Parallel Differential Setup(2) Mux Parallel Differential Hold(2) Mux Parallel Single-Ended Setup(2) Mux Parallel Single-Ended Hold(2) Min. 2.7 45 200 0 150 50 +200 +200 45 Tcyc+650 -(Tcyc+250) Tcyc+850 -(Tcyc+50) -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- 100 -- Max. -- 55 -- -- -- -- +800 +1200 55 -- -- -- -- 120 500 Unit GHz % ps ps ps ps ps ps % ps ps ps ps ps 50 to VCC - 2V (20% to 80%) Condition Output Rise/Fall Times MCKOUT, MSOUT, MSYNOUT All Others NOTES: 1. Operating temperature range from -40C to +85C. 2. Tcyc = the period of the clock being fed into MTXCLK. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 10 Micrel, Inc. SY87724L TIMING WAVEFORMS tDSDS DSIN tDSFS DCKIN DFMIN Valid Valid tDSDH tDSFH DPOUTCK tDPDP DP0-4 tDPSP DPOUTCK+ DP0-4+ DP5-9 tMPDS MPF0-4 MPINCK Valid tMPDH tMPSS MP0-9 MPINCK+ Valid tMPSH tDCKPWH DCKIN tDCKPWL tMCKPWH MTXCLK tMCKPWL M9999-031506 hbwhelp@micrel.com or (408) 955-1690 11 Micrel, Inc. SY87724L TIMING APPLICATION EXAMPLE MPF0-4 Valid 1750 1350 MPINCK x MTXCLK y MPF0-9 Valid 1950 1150 MPINCK x MTXCLK y NOTES: 1. MTXCLK = 1Gbps 2. Time "x" is approximately equal to time "y." 3. Setup and hold for MPF0-4 is conditioned on the MTXCLK rising edge just prior to the MTXCLK rising edge that causes an MPINCK rising edge. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 12 Micrel, Inc. SY87724L 80-PIN LQFP-PQ2 (DIE UP) (H80-1) +0.05 -0.05 +0.002 -0.002 +0.5 -0.5 +0.020 -0.020 +0.5 -0.5 +0.020 -0.020 +0.15 -0.15 +0.006 -0.006 +0.06 -0.10 +0.002 -0.004 Package EP- Exposed Pad Rev. 00 Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 80-Pin EPAD-TQFP Package MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL USA + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-031506 hbwhelp@micrel.com or (408) 955-1690 13 |
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